Equivalence checking (EC) can be performed between circuits such as combinational and/or sequential logic circuits. Many design flows involve a large number of EC runs on the same two designs, often with only local or incremental changes to one or both designs. Local or incremental design changes can mean that from one EC run to the next, many of the same common logic cone pairs are being compared.
To date, most effort has been spent on improving the compare and mapping algorithms themselves.
It would be desirable to take advantage of similarities with past multiple equivalence checking runs to speed up equivalence checking.